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The last 5 uploaded publications
A Systematic Approach to Blocking Convolutional Neural Networks
Xuan Yang, Jing Pu, Blaine Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan‐Kelley, Ardavan Pedram, Mark Horowitz (2016). A Systematic Approach to Blocking Convolutional Neural Networks. arXiv (Cornell University), DOI: 10.48550/arxiv.1606.04209.
Preprint300 days agoAHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po‐Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James J. Thomas, Nikhil Bhagdikar, David Durst, Zachary Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjølstad, Priyanka Raina (2022). AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. ACM Transactions on Embedded Computing Systems, 22(2), pp. 1-34, DOI: 10.1145/3534933.
Article300 days agoEvaluating programmable architectures for imaging and vision applications
Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz (2016). Evaluating programmable architectures for imaging and vision applications. , DOI: 10.1109/micro.2016.7783755.
Article300 days agoAmber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James J. Thomas, Kavya Sreedhar, Po‐Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D’Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina (2022). Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 70-71, DOI: 10.1109/vlsitechnologyandcir46769.2022.9830509.
Article300 days agoCreating an Agile Hardware Design Flow
Rick Bahr, Clark Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjølstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Raj Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James J. Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang (2020). Creating an Agile Hardware Design Flow. , DOI: 10.1109/dac18072.2020.9218553.
Article300 days ago