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Get Free AccessA folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10/sup -15/ and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.
Jared Zerbe, C. Werner, Vladimir Stojanović, F. Chen, J. Wei, G. Tsang, Donggeon Kim, William Stonecypher, A. Ho, T.P. Thrush, Ravi Kollipara, Mark Horowitz, Kevin Donnelly (2003). Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE Journal of Solid-State Circuits, 38(12), pp. 2121-2130, DOI: 10.1109/jssc.2003.818572.
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Type
Article
Year
2003
Authors
13
Datasets
0
Total Files
0
Language
English
Journal
IEEE Journal of Solid-State Circuits
DOI
10.1109/jssc.2003.818572
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