(Raw Data Set) High-speed, two-stage operational transconductance amplifier without Miller capacitor, suitable for large capacitive load

Abstract

A two-stage Class A-AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two-stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two-stage amplifier maintains a 45 degrees phase margin (PM) over any load capacitance. This is achieved through a MOSFET-based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR-. Post-layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/mu s, a gain-bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6 degrees, while consuming only 103.5 mu W. Reducing the CL to 10 pF reduces the PM to 47.6 degrees, while increasing the gain-bandwidth and average slew rate to 82.9 MHz and 142.6 V/mu s respectively. This article presents a novel two-stage Class A-AB OTA designed to overcome large capacitive loads. Unlike conventional designs, it maintains a minimum 45 degrees phase margin across all capacitive loads using a MOSFET-based RC network, eliminating the need for a Miller capacitor. This innovative approach is further complemented by dual nMOS/pMOS stages for direct output drive, improving both positive and negative slew rates. image