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Fault and Soft Error Tolerant Delay-Locked Loop

Abstract

We present in this paper the first fault and soft error tolerant Delay-Locked Loop (DLL) design, useful for the clock synchronization in a chip incorporating heterogeneous functional dies. In this robust DLL design, we introduce a powerful timing correction scheme to remedy the timing shortfall in a naive Triple-Module Redundancy (TMR) architecture. Post-layout simulation results using a 90nm CMOS process is used to verify the performance of this design. In addition to the tolerance of randomly injected faults or soft errors, the Maximum Phase-Error can be improved tremendously from 117ps to just 17ps by the proposed timing correction scheme.

article Proceedings Paper
date_range 2020
language English
link Link of the paper
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Featured Keywords

Delay-Locked Loop
Fault Tolerant
Soft Error Tolerant
Timing Correction Scheme
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