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  5. Understanding sources of inefficiency in general-purpose chips

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Article
English
2010

Understanding sources of inefficiency in general-purpose chips

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English
2010
ACM SIGARCH Computer Architecture News
Vol 38 (3)
DOI: 10.1145/1816038.1815968

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Mark Horowitz
Mark Horowitz

Stanford University

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Rehan Hameed
Wajahat Qadeer
Megan Wachs
+6 more

Abstract

Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance and energy efficiency. This paper explores the sources of these performance and energy overheads in general-purpose processing systems by quantifying the overheads of a 720p HD H.264 encoder running on a general-purpose CMP system. It then explores methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding. We evaluate the gains from customizations useful to broad classes of algorithms, such as SIMD units, as well as those specific to particular computation, such as customized storage and functional units. The ASIC is 500x more energy efficient than our original four-processor CMP. Broadly applicable optimizations improve performance by 10x and energy by 7x. However, the very low energy costs of actual core ops (100s fJ in 90nm) mean that over 90% of the energy used in these solutions is still "overhead". Achieving ASIC-like performance and efficiency requires algorithm-specific optimizations. For each sub-algorithm of H.264, we create a large, specialized functional unit that is capable of executing 100s of operations per instruction. This improves performance and energy by an additional 25x and the final customized CMP matches an ASIC solution's performance within 3x of its energy and within comparable area.

How to cite this publication

Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz (2010). Understanding sources of inefficiency in general-purpose chips. ACM SIGARCH Computer Architecture News, 38(3), pp. 37-47, DOI: 10.1145/1816038.1815968.

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Publication Details

Type

Article

Year

2010

Authors

9

Datasets

0

Total Files

0

Language

English

Journal

ACM SIGARCH Computer Architecture News

DOI

10.1145/1816038.1815968

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