Transistors Formed from a Single Lithography Step Using Information Encoded in Topography

Abstract This paper describes a strategy for the fabrication of functional electronic components (transistors, capacitors, resistors, conductors, and logic gates but not, at present, inductors) that combines a single layer of lithography with angle‐dependent physical vapor deposition; this approach is named topographically encoded microlithography (abbreviated as TEMIL). This strategy extends the simple concept of ‘shadow evaporation’ to reduce the number and complexity of the steps required to produce isolated devices and arrays of devices, and eliminates the need for registration (the sequential stacking of patterns with correct alignment) entirely. The defining advantage of this strategy is that it extracts information from the 3D topography of features in photoresist, and combines this information with the 3D information from the angle‐dependent deposition (the angle and orientation used for deposition from a collimated source of material), to create ‘shadowed’ and ‘illuminated’ regions on the underlying substrate. It also takes advantage of the ability of replica molding techniques to produce 3D topography in polymeric resists. A single layer of patterned resist can thus direct the fabrication of a nearly unlimited number of possible shapes, composed of layers of any materials that can be deposited by vapor deposition. The sequential deposition of various shapes (by changing orientation and material source) makes it possible to fabricate complex structures—including interconnected transistors—using a single layer of topography. The complexity of structures that can be fabricated using simple lithographic features distinguishes this procedure from other techniques based on shadow evaporation.