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Get Free AccessA bstract : Simulations were performed to assess the prospective performance of a 16 Kbit nanowire‐based electronic nanomemory system. Commercial off‐the‐shelf microcomputer system modeling software was applied to evaluate the operation of an ultra‐dense storage array. This array consists of demonstrated experimental non‐volatile nanowire diode switches, plus encoder‐decoder structures consisting of demonstrated experimental nanowire‐based nanotransistors, with nanowire interconnects among all the switching devices. The results of these simulations suggest that a nanomemory of this type can be operated successfully at a density of 10 11 bits/cm 2 . Furthermore, modest device alterations and system design alternatives are suggested that might improve the performance and the scalability of the nanomemory array. These simulations represent early steps toward the development of a simulation‐based methodology to guide nanoelectronic system design in a manner analogous to the way such methodologies are used to guide microelectronic system design in the silicon industry.
Matthew M. Ziegler, Carl A. Picconatto, James C. Ellenbogen, André DeHon, Deli Wang, Zhaohui Zhong, Charles M. Lieber (2003). Scalability Simulations for Nanomemory Systems Integrated on the Molecular Scale. Annals of the New York Academy of Sciences, 1006(1), pp. 312-330, DOI: 10.1196/annals.1292.022.
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Type
Article
Year
2003
Authors
7
Datasets
0
Total Files
0
Language
English
Journal
Annals of the New York Academy of Sciences
DOI
10.1196/annals.1292.022
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