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Get Free AccessMIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.
Mark Horowitz, Paul Chow, D. Stark, Richard Simoni, Arturo Salz, Steven A. Przybylski, John L. Hennessy, Glenn Gulak, Anant Agarwal, John M. Acken (1987). MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache. IEEE Journal of Solid-State Circuits, 22(5), pp. 790-799, DOI: 10.1109/jssc.1987.1052815.
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Type
Article
Year
1987
Authors
10
Datasets
0
Total Files
0
Language
English
Journal
IEEE Journal of Solid-State Circuits
DOI
10.1109/jssc.1987.1052815
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