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Get Free AccessThis paper addresses timing and glitch detection problems involving charge sharing in acyclic resistor capacitor networks. Solutions to these problems are proposed and applied to real designs. Results are reported and compared with SPICE simulation. Our algorithms are intended for use in switch level simulators and timing verifiers which model transistors in digital VLSI designs as linear resistors. Computational complexity of our methods is also investigated. (Author)
Chang-Yung Chu, Mark Horowitz (1983). Charge Sharing Models for MOS Circuits..
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Type
Article
Year
1983
Authors
2
Datasets
0
Total Files
0
Language
en
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