Automated synthesis of a high-speed adder

At the gate level, the Kogge-Stone adder (KSA) is known to outperform many high-speed adders including other parallel prefix adders in terms of the speed performance. This paper presents a methodology to synthesize a new high-speed adder automatically, called the AHSA, using a logic synthesis tool. We describe what adder architectures can be input to a logic synthesis tool and what synthesis constraints should be specified so that the AHSA can be automatically synthesized. The AHSA is significant since it has a speed similar to that of the KSA while requiring less area and dissipating less power. In this paper, 32-bit addition serves as an example, and various adders belonging to different architectures were synthesized using a 28 nm Synopsys CMOS standard cell library. The design metrics estimated show that while the KSA has a 5.2% reduced delay than the AHSA, the AHSA occupies 29.1% less area and consumes 9.6% less power than the KSA. In terms of the figures of merit used for a digital circuit design such as power-delay product (PDP), area-delay product (ADP), and power-delay-area product (PDAP), the AHSA achieves a 4.7% reduced PDP, a 25.2% reduced ADP, and a 32.4% reduced PDAP compared to the KSA. This paper demonstrates that when speed is the key factor in an adder design, the AHSA is preferable to the KSA. Moreover, the AHSA is shown to be significantly faster than other high-speed adders at the gate level.