Asynchronous monotonic multiplexer

Among input-output (IO) mode asynchronous circuits, indicating circuits are more popular and robust. However, they may not be efficient in design metrics such as cycle time, area, and power dissipation. In contrast, monotonic circuits, which are also IO mode asynchronous circuits but less explored, can potentially optimize the design metrics better than indicating circuits. Recent studies have demonstrated that monotonic circuits outperform indicating circuits in arithmetic operations like addition and multiplication. While monotonic circuits may be labeled theoretically less robust than indicating circuits, their operation is similar in practice. This article presents a novel, compact monotonic IO mode asynchronous multiplexer. The multiplexer is significant in digital circuits as it has applications across various domains including communication systems, digital signal processing, memory addressing, etc. We considered dual-rail encoding for the multiplexer and employed four-phase handshaking. Two four-phase handshaking schemes are available namely, return-to-zero (RtZ) handshaking and returnto-one (RtO) handshaking, and we considered both for this work. Compared to an optimized early output quasi-delay-insensitive multiplexer, which is derived by modifying a strongindication multiplexer and represents the best among the existing designs, the proposed monotonic multiplexer achieves a 67% (69%) reduction in latency, an 84% (84%) reduction in area, and a 66% (67%) reduction in power for RtZ (RtO) handshaking. Since the multiplexer is a small component, its effectiveness should be evaluated by integrating it into a circuit setup. In this context, we used existing multiplexers and the proposed multiplexer to realize IO mode asynchronous 32-bit carry select adders (CSLAs) while keeping the compute element, namely the full adder consistent. We estimated the design metrics of CSLAs incorporating different multiplexers, implemented using a 28-nm bulk CMOS process technology. The CSLA utilizing the proposed monotonic multiplexer achieved a 43% (44%) reduction in cycle time and a 28% (28%) reduction in area compared to the CSLA utilizing an early output quasidelay-insensitive multiplexer for RtZ (RtO) handshaking with no power penalty.