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Get Free AccessA Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm×8.5mm chip in a 2μm, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.
Mark Horowitz, John L. Hennessy, Paul Chow, P.G. Gulak, John M. Acken, Anant Agarwal, Chorng-Yeung Chu, Scott McFarling, Steven A. Przybylski, Stephen Richardson, Arturo Salz, Richard Simoni, D. Stark, Peter Steenkiste, Steve Tjiang, Malcolm J. Wing (1987). A 32b microprocessor with on-chip 2Kbyte instruction cache. , pp. 30-31, DOI: 10.1109/isscc.1987.1157215.
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Type
Article
Year
1987
Authors
16
Datasets
0
Total Files
0
Language
English
DOI
10.1109/isscc.1987.1157215
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