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  5. A 20 MIPS Peak Microprocessor with On-Chip Cache,

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Article
en
1984

A 20 MIPS Peak Microprocessor with On-Chip Cache,

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en
1984
oai.dtic.mil/oai/oai?&verb=getRecord&…

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Mark Horowitz
Mark Horowitz

Stanford University

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Mark Horowitz
John L. Hennessy
Paul Chow
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Abstract

MIPS-X is a 32b microprocessor with an on-chip 16Kb instruction cache. The chip is implemented in a 2 micron drawn channel length, 2-layer metal CMOS technology, contains 150K transistors in an 8mm by 8.5mm die, and has 84 signal pins and 24 power pins. At a peak operating frequency of 20MHz the chip will dissipate less than 2W. (Author)

How to cite this publication

Mark Horowitz, John L. Hennessy, Paul Chow, P.G. Gulak, John M. Acken (1984). A 20 MIPS Peak Microprocessor with On-Chip Cache,.

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Publication Details

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Article

Year

1984

Authors

5

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0

Total Files

0

Language

en

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